1. Field of the Invention
The present invention relates to cache circuitry for a data processing apparatus, a data processing apparatus including such cache circuitry, and a method for prefetching data for storing in the cache circuitry.
2. Description of the Prior Art
A data processing apparatus will typically include one or more data processing units which are operable to perform data processing operations on data values stored in memory. Since accesses to memory are relatively slow, and henco are likely to adversely impact the performance of the processing unit, it is known to provide one or more caches within the data processing apparatus for storing a subset of the data values so that they can be made available to the processing unit more quickly than if instead they had to be accessed directly from memory.
When a processing unit wishes to access a data value, it will typically issue an access request specifying an address in memory of the data value required to be accessed. A cache receiving that access request will typically be arranged to determine from the specified address, or at least from a portion thereof, whether the data value the subject of the access request is stored within one of the cache lines of the cache (this being referred to as a hit condition), and if so to allow the data value to be accessed in the cache. For a write access, this will involve updating the relevant data value within the identified cache line, whereas for a read access this will involve returning to the processing unit the data value as read from the identified cache line.
If on receipt of an access request, the cache determines that the data value the subject of the access request is not present in the cache (referred to as a miss condition), then the cache may be arranged to perform a linefill operation in order to retrieve into the cache a cache line's worth of data from memory, including the data value the subject of the access request, so that the data value can then be accessed directly from the cache. As part of such a linefill procedure, it will be necessary to select a cache line in which this new content is to be stored. If that selected cache line is currently storing data relating to a write through region of memory, any updates to that cache line's data will also have been made to memory, and accordingly there is no need to output the current contents of that cache line to memory before overwriting it with the new content retrieved as part of the linefill procedure. However, if the current contents of that cache line relate to a write back region of memory, it will additionally be necessary as part of the linefill procedure to evict the current cache line's contents to memory to ensure that memory is updated to reflect any changes that have been made to the current content of the cache line.
It is known within data caches to provide mechanisms that sock to detect patterns of accesses, and upon such detection to seek to prefetch data into the cache in the expectation that that data will subsequently be requested by the processing unit. Such mechanisms can be employed irrespective of whether the cache is arranged as a write through cache or a write back cache, or indeed as a combination of both.
Typically, such prefetch mechanisms perform linefill operations to prefetch from memory data at addresses determined by extrapolating from the addresses specified by access requests in which the pattern has been detected. For example, if a sequence of access requests are observed where the first access is to address X, the next access is to address X+2, and the following access is to address X+4, a stride of two may be detected, and cause the prefetch circuitry to be activated to start prefetching data from addresses X+6, X+8, etc.
In large caches, such as those used to form level two caches within a data processing apparatus, it is known for the prefetch circuitry to issue a sequence of addresses, with the data values returned being allocated into corresponding cache lines. If the predicted accesses then take place with respect to that cache, the data values will already be stored in the cache, and a cache hit will immediately be detected on performing a cache lookup. This optimises the speed for handling such access requests. However, since the accesses corresponding to the prefetched data are only predicted, they may in fact not occur, and in that event the cache will have been polluted with data that is not actually needed, thereby reducing the efficiency of the cache. For relatively large caches, such pollution has not been considered to be a significant problem.
However, for smaller caches, pollution is a much more significant problem, and can have a much greater adverse effect on performance of the cache. Accordingly, in smaller caches, such as for example those used to implement level one caches, prefetch circuitry once activated will typically perform one linefill request at a time, with the data obtained as a result of that linefill request being stored in a linefill buffer, but not at that time being allocated to the cache. Instead, the data is only allocated from the linefill buffer into the cache if the processing unit does in fact issue an access request seeking to access that prefetched data. Thereafter, the prefetch circuitry may optionally issue another linefill request to prefetch another cache line's worth of data for storing in the linefill buffer. Whilst such an approach has some impact on the speed of handling the access request, since the data is not already in the cache array at the time the access request is received in the cache, and instead has to either be read from the linefill buffer or read after the data has been allocated into the cache array, it does avoid the earlier-mentioned pollution problem.